TSMC Advanced Packaging Evolution History

Traditional packaging

The metal pitch (Metal Pitch) of packaging between chips has stayed at 110um, and has not improved in 20 years. What is metal spacing? Generally, the chip we get (such as CPU) is actually a complete chip module. A chip in the strict sense is a die cut from a wafer.

According to the traditional packaging steps, these bare chips need to be placed on the substrate (Sustrate), the pins and leads are drawn out, and then they are fixed and packaged into a shell before they can be used in actual circuits.

Advanced packaging is not a new concept. Looking back on history, the year 2000 was a turning point for advanced packaging. Starting from this year, packaging has shifted from traditional wire bonding and flip-chip methods to “wafer-level packaging.” As early as 2008, TSMC established the Integrated Interconnect and Packaging Technology Integration Department (IIPD) to enter advanced packaging.

TSMC Advanced Packaging History

Shang-yi Chiang’s vision

In 2005, as the chip manufacturing process reached the 65nm mark, TSMC captured 50% of the global chip foundry market. The only competitor behind it seemed to be Samsung, which was struggling to catch up. Morris Chang, who felt that the situation was set, announced He stepped down as CEO and retired to the second line, but Chiang Shangyi, then president of TSMC Technology, was thinking about a problem.

The metal spacing that Shang-yi Chiang is thinking about is actually the spacing between leads. For example, the exchange of data between the CPU and the memory relies on these leads. Theoretically, the greater the number of leads, the more efficient the connection between different chips and the better the overall performance. However, since the leads are made of metal, once the density increases, the power consumption and heat generation will increase.

In this context,Shang-yi Chiang conceived a bold plan: instead of risking increasing the density of leads, it is better to package two wafers on a silicon wafer. Due to the closer physical distance, the delay problem in electrical signal transmission is improved, and metal The disadvantages caused by the material are also easily solved. From “Seal first, then seal” to “First fight, then seal”, the former is now classified as traditional packaging, while the latter is a hot concept in recent years – “advanced packaging”.

Problem occurs

Moore’s Law states that the number of transistors that can be accommodated on a chip doubles every 18-24 months. Over the past few decades, the semiconductor industry has developed rapidly in accordance with Moore’s Law, from 130nm to 90nm, and from 65nm to 40nm, as smoothly as passing a game.

For foundries, compared with the performance improvements brought by the chip manufacturing process, the performance improvements brought by heavy investment in advanced packaging are really too low in cost performance. In addition, Shang-yi Chiang retired with Morris Chang in 2006, and the advanced packaging solution was not implemented.

But in 2009, the industry began to conquer the 28nm process, and engineers realized the seriousness of the problem: the unit manufacturing cost of transistors rose instead of falling, and the cost-effectiveness of process upgrades to improve performance began to decrease. In other words, Moore’s Law is failing.

Start developing advanced packaging

In 2009, Morris Chang returned as CEO and invited back Shang-yi Chiang, who had retired. The 28nm process is the beginning of the countdown to the death of Moore’s Law and the starting point for TSMC’s advanced packaging. In 2009, with Morris Chang’s approval, Shang-yi Chiang started the research and development of advanced packaging technology with an investment of US$100 million in equipment and a team of more than 400 engineers.

For the “fan-out wafer-level packaging” that attracted attention at the time, Intel and Samsung ranked second and third in terms of number of patents, and TSMC did not even make the top ten.

TSMC’s first advanced packaging technology, CoWoS, was born in this atmosphere. CoWoS is a combination of CoW and oS: CoW stands for Chip on Wafer, which refers to the process of assembling bare chips on a wafer, and oS stands for on Substrate, which refers to the process of being packaged on a substrate – this was also proposed by Shang-yi Chiang in 2006 Conception.

First customer order

Compared with other similar technologies, the outstanding advantages of TSMC CoWoS are reflected in the way the die is connected:

The wafer loaded with bare chips is called a silicon interposer by TSMC. In the silicon interposer, TSMC uses micro-bumps (ubmps), rewiring (RDL) and other technologies to replace traditional wire bonding for connection between die. Increased interconnection density and data transmission bandwidth.

However, the fledgling CoWoS was once in an embarrassing situation. In 2011, TSMC received an order from Xilinx, a major FPGA manufacturer. With CoWoS and jointly developed through silicon via (TSV) and other technologies, TSMC successfully spliced four 28nm FPGA chips together and launched the largest FPGA chip in history. But this was also the only order received by TSMC’s advanced packaging project team throughout 2011.

CoWoS is too expensive

NVIDIA – Since GPU calculations require frequent communication with memory to obtain and store data, the tolerance for latency is lower and the bandwidth requirements are higher. Unexpectedly, NVIDIA’s enthusiasm waned. Qualcomm told Shang-yi Chiang: CoWoS is too expensive.

“I am only willing to spend 1 cent/square millimeter for this technology.” With these words, Shang-yi Chiang found Yu Zhenhua and got the answer that the current price of CoWoS is 7 cents/square millimeter, confirming that the 6-fold gap is Reasons for customer hesitation.

InFO came

Such a large cost gap will inevitably not be eliminated through technology in a short time. TSMC decided to “subtract” CoWoS and develop a cheaper version of CoWoS technology. Yu Zhenhua, who has rich experience in manufacturing and packaging, quickly handed over the alternative plan-InFO.

The reason why CoWoS technology is expensive is mainly because of the silicon interposer, which is essentially a silicon wafer, and wiring is required to make connections in the middle, which is naturally very costly. InFO replaced the silicon interposer with other materials, sacrificing connection density, but in exchange for a significant reduction in cost.

Begin to be accepted by customers

Apple adopted

Samsung also relied on its exclusive PoP packaging technology to stack memory chips directly on top of the SoC, thereby greatly reducing the chip area and winning Apple’s super large order for the A series of self-developed mobile SoCs.

Samsung mobile phones are conquering the global market and becoming Apple’s biggest competitor. Around 2013, while fighting a lawsuit with Samsung, Apple gave the chip order to TSMC. In this context, InFO, which has surpassed PoP packaging in both chip reduction effect and cost performance, has become a turning point for TSMC to be “righted up”. In 2016, the iPhone 7 equipped with Apple’s latest A10 mobile SoC was launched, all manufactured by TSMC.

Become the mainstream of high-efficiency chips

With Apple taking the lead, chip manufacturers that had been hesitant due to price issues finally got on board with confidence and boldness. Major customers rushed to adopt CoWoS package. Nvidia, AMD, Google, and even competitor Intel all used it in their own high-performance chips.

In 2023, AI chips will continue to rise, and the demand for CoWoS for Nvidia GPUs will soar from the 30,000 pieces estimated at the beginning of the year to 45,000 pieces, forcing them to place additional orders in advance.

TSMC’s CoWoS

From scratch

In 2011, TSMC developed the first generation of CoWoS packaging technology, which was the original origin. At that time, CoWoS used a silicon (Si) substrate as an intermediate substrate (interposer) to integrate multiple chips into one package, achieving higher interconnect density and better performance.

Since then, CoWoS packaging has continued to improve and develop. Now CoWoS is a 2.5D integrated production technology, which is a combination of CoW and WoS: CoW is stacking wafers on wafers (Chip-on-Wafer), while WoS is wafers on substrates (Wafer-on-Wafer). Substrate), integrated into CoWoS.

Three types of CoWoS packaging technologies

According to different interposers, TSMC divides CoWoS packaging technology into three categories: the first category, CoWoS-S, uses Si substrate as the interposer; the second category, CoWoS-R, uses the redistribution layer (RDL) as the interposer; The third type of CoWoS-L uses chiplets and RDL as interposers.

Future route

In the latest speech, Hou Shangyong, director of TSMC’s high-efficiency packaging integration department, said that as the best solution that can meet all conditions, TSMC’s advanced packaging focus will gradually shift from CoWoS-S to CoWoS-L, and is called CoWoS-L. It is a key technology for the future blueprint.

Hou Shangyong believes that because the cost of the top die (Top Die) is very high, CoWoS-L is the best solution that can meet all conditions better than CoWoS-R and CoWoS-S, and because of its flexibility, it can achieve different results in its interposer layer. Quality integration will have its specialized size and function. CoWoS-L is compatible with a wide range of high-performance top-end chips, such as advanced logic, SoIC and HBM.

Crazy factory expansion

Existing and future planned factories

In addition to actively carrying out global expansion of general wafer factories, in recent years, TSMC has also extended its factory expansion to the field of semiconductor packaging. For the details of this part, as well as the list of TSMC’s current and future planned factories, the focus of production, the official completion timetable and other details, please refer to my post of: “”How many fabs and houses does TSMC have currently and in the future?“

The latest packaging factory announced

TSMC announced in August 2024 that it had purchased Innolux’s Tainan 4 fab (5.5-generation fab), sparking heated discussion in the market. In mid-October 2024, it was reported in the industry that TSMC had decided to purchase another old Innolux factory in Nanke, mainly to meet the demand for CoWoS driven by AI. The industry estimates that after the purchase of the plant, the fastest timetable will be 2026.

TSMC Advanced Packaging — credit: edn.com

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