Comparison of TSMC, Intel, and Samsung’s new process roadmaps for future chips

Process

Recently, I have seen several articles discussing Intel’s and TSMC’s process comparison schedules. Many of them are not bad, but they are too deep dive. I want to pick the most important ones. In addition to the previous public information released by Intel (ticker: INTC), Samsung (ticker: SSNLF), and TSMC (ticker: TSM), I will organize it for interested investors and write this article that you see. Regarding Intel’s progress, everyone is very concerned, here are the official official documents of Intel for reference.

New process schedules for future chips

20182019202020212022202320242025
TSMC7nm 6nm, 5nm4nm3nm (FinFET)3nm+ (FinFET)2nm (GAA) Pilot run2nm (GAA)
Samsung8nm5nm, 4nm3nm (GAE) 3nm+ (GAA) 2nm (GAA)
IntelIntel 10Intel 7Intel 4 (7nm),
Intel 3(2H of 2023)
Intel 20A
(Early 2024)
Intel 18A
(2H of 2025)
Based on TSMC, Samsung, and Intel’s offical data

Intel

Please note the following three points:

  • After Intel’s new CEO Kissinger took office this year, he launched the IDM 2.0 plan to return to semiconductor foundry business, and Intel changed its process naming rules in 2021. Because its naming method in the past is easy to misunderstand (Please refer to the table comparison table in the “Transistor Density Comparison” section below, you will understand why), for example:
    • Intel’s 10nm was actually equal to TSMC and Samsung’s 7nm
    • Intel’s 7nm was actually equal to TSMC and Samsung’s 5nm
  • And now
    • Intel 7, that is Intel’s Enhanced SuperFin
    • Intel 4, that is Intel’s 7nm
    • Intel 3, that is Intel’s 3nm
    • Intel 20A is Intel’s 2nm; where A means angstroms, and 10 angstroms equals 1 nanometer.
    • Intel 18A is also Intel’s 2nm (2nm’s enhanced version)
  • Intel 4 will be mass-produced in the first half of 2023, and Intel 3 will be mass-produced in the second half of 2023.
  • Intel publicly announced on 4/24/2022 that it will bring forward all future advanced process plans, saying:
    • 4nm launch in the second half of 2022
    • 3nm launch in 2023
    • 20A (2nm) production in early 2024
    • 18A (1.8nm) in the second half of

Samsung

Samsung’s 3-nanometer timeframe:

  • Samsung’s first 3-nanometer has been successfully developed and was production in second quarter of 2022
  • The improved version of 3-nanometer (aka 3nm+) mass production schedule has been extended to 2023, according to Samsung’s official statement, which is one year behind TSMC; this will seriously damage Samsung’s wafer foundry business.

TSMC

Although it has been repeatedly reported that it has encountered technical problems and yield problems, TSMC’s 3nm commercial mass production time has been officially reconfirmed by TSMC to be in the second half of 2022.

Why the table matters?

Compare the schedule table of the above three manufacturers’ process roadmap:

  • Intel has mass-produced Intel 7 in 2021, which is equivalent to TSMC’s 7nm. TSMC has already mass-produced in 2018, which is three years behind.
  • In the first half of 2023, Intel 4 will be mass-produced, which is equivalent to TSMC’s 4nm. TSMC has already mass-produced in 2020, which is about two and a half years behind.
  • By 2023, Intel plans to mass-produce Intel 3, which is equivalent to TSMC’s 3nm, and TSMC will mass-produce its 3nm in 2022. At this time, Intel is almost one year behind.
  • When it comes to the 2nm process, Intel plans to catch up with TSMC’s 2nm process schedule in 2024, a year in advance. This also means that it is very difficult to update the technology on the next-generation process just in one year. TSMC generally upgrades the next-generation technology in two years. Specially , Intel still has room for improvement in the yield rate, or it is still possible delayed. Moreover, according to Intel’s repeated backwardness in manufacturing processes in the past, the industry generally does not believe that Intel is capable of make it.

I previously emphasized the following two points in my previous article Intels current difficult dilemma :

  • Intel and TSMC have at least two generations of semiconductor process gaps. “Even if the best, everything goes smoothly,” it will not be possible without 4 to 5 years for Intel to fill the gaps.
  • “First, make up for the process gap behind TSMC, and talk more about the rest.”

Note: no surprises! After I have published this article; On December 10, 2021, Intel’s CEO Gelsinger believes that it will take at least five years for the company to turnaround, which is the same as my opinion. This is not a secret, the industry insiders or Wall Street’s more senior semiconductor analysts also think so.

The deployment of GAA

GAA (Gate All Around) is the core technology of the next generation of chip manufacturing. Generally speaking, TSMC is the last of the three to deploy it, and it was first introduced at TSMC’s 2nm process. The following is the time schedule for the three manufacturers to deploy GAA, and the comparison table of the imported nodes:

GAA nameProcessSchedule
IntelRobbonFET20A2024
IntelRobbonFET 18A2025
TSMCGAAFETN2/2nm2025
SamsungMCBFET3GAE2022
SamsungMCBFET 3GAP2023

Transistor density comparison

Four vendors head-to-head

By the end of 2021, the data published by each company will be the main basis. The following table is from WikiChip, and the unit of value is millions of transistors/square meter.

Process nameIBMTSMCIntelSamsung
22nm16.50
16nm/14nm 28.8844.6733.32
10nm 5310652
7nm9718095
5nm173300127
3nm290520170
2nm/20A333.33490
*Estimated Logic Density

Intel

In the previous section of “New process schedules for future chips”, we said that Intel’s previous naming method is misleading. The reason is that you will understand if you use this table comparison table to explain:

  • Intel’s 16nm/14nm transistor is 44.67, which is roughly equivalent to TSMC’s 52.51 of 10nm.
  • Intel’s 10nm transistor is 100.76, which is roughly equivalent to TSMC’s 7nm transistor of 91.20
  • Intel’s 7nm transistor is 237.18, which is roughly equivalent to TSMC’s 5/4nm of 171.30

You now know why since 7-8 years ago, Intel saw their own chip process advancement speed has been surpassed by TSMC and Samsung, and find out some words that made sense at the time and technically, “We Intel’s 16nm /14nm is equal to TSMC’s 10nm.” After another three or four years later, the statement became “Our Intel’s 10nm is equal to TSMC’s 7nm”, so we are not behind! Please note that at this time, it is actually about 1-1.5 generations behind TSMC.

But when Intel’s clichés were moved out at this moment after 10 years, investors were fed up. Because it is not only one generation behind, it is 2-2.5 generations behind (In chip process generation, one generation is about 2-3 years behind), no matter how round it is, it cannot be justified.

Samsung

What about the Samsung part? Although Samsung’s 3nm has been successfully developed and a small part of commercial trial production has been successful. However, from the perspective of key indicators such as transistor density and power consumption, Samsung’s 3nm process is actually comparable to TSMC’s 4nm process and Intel’s Intel 4 (formerly Intel’s 7nm process).

What about 2 nanometer and below ?

Technical challenges

The Belgian Microelectronics Research Center (IMEC) said that Moore’s Law will not end, but must be contributed by many parties. IMEC has proposed the semiconductor process technology and chip design path from 1 nanometer to 2 angstroms, continuing Moore’s Law.

Currently, these efforts include:

  • Overall Architecture: FinFET Devices, Boards, Atomic Channel Devices
  • New Materials: Using new materials, tungsten or molybdenum, to fabricate gates equivalent to a few atoms in length for 1-nanometer and 4-angstrom and 2-angstrom structures.
  • A new generation of EUV extreme ultraviolet exposure machine: ASML’s new generation of High-NA EUV exposure machine has been introduced. Currently, customers are installing the prototype of the High-NA EUV exposure machine, which is expected to be put into commercial use in 2024. It is believed that exposure tools will extend Moore’s Law below the 1nm node.
  • GAA Architecture: Starting at 2nm, the GAA architecture with stacked nanosheets is the most likely concept. The Forksheet architecture developed by IMEC can scale gates beyond 1nm.

The key among them is ASML’s new generation of EUV extreme ultraviolet exposure machine. Regarding this company, I suggest you refer to my other blog article “ASML, who dominate TSMC’s fate“.

Actions of major manufacturers

The current processes below 1 nanometers are still in the “very early stage”, which is a period of research and exploration. Please refer to the following collation:

Company NamePartnersTechnologies and prelimilary announcement
TSMCMITIn June 2022, the original 3nm process R&D team will be converted into a 1.4nm R&D team.
In May, 2021, TSMC and MIT announced that it will break through the limit of 1 nanometer process with bismuth metal characteristics, and reach below 1 nanometer.
SamsungIBMAt IEDM 2021 event, IBM and Samsung co-announced VTFET chip design technology. Stacking the transistors in a vertical manner and allowing the current to flow vertically also increases the number density of transistors again, greatly improves the efficiency of power use, and breaks the bottleneck of the 1 nanometer process.
IntelReady for mass production of 1.8nm process in the second half of 2024
process

What about the yield comparison?

I post another article on my blog about the advanced process and the yield rate of these three companies. Please refer to the article “Comparison of TSMC, Samsung, Intel’s Yield and Advanced Process“.

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2 thoughts on “Comparison of TSMC, Intel, and Samsung’s new process roadmaps for future chips”

  1. Hi Andy,
    Thanks for this great post. I’m quite interested in why TSMC has so great margin except its market share. By the way, I read your posts here and your webste and investment performance. It’s awesome! Any plan to publish a English investment book like you had in Chinese?

    1. Hi Bill,

      In 2021 shareholders meeting (July 2021), TSMC chainman Mark Liu confirmed company is confident will maintain long-term 50% of gross margin, although there will be many new fabs built in US, Japan, Taiwan in the coming years. Moreover, bescause almost all of TSMC’s production fabs are in Taiwan and China, the operating margin is at least 30% lower than US peers. This is the root cause why TSMC could have net profit margin of 37.7%, and operating margin of 41.4% (Q1 2021), as compare to most US foundry’s proximately 25% net profit margin and 28% operating margin.

      Yes, I’ll publish my English physical book some time this year, hopefully everyone could buy physical book on Amazon by 2022. I’ll post the launch day here, once available.

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